module div_clk(input iclk,
               input rst_n,
					output oclk
					);//偶数分频
parameter div_num = 4;//分频系数
reg [31:0] div_cnt;//分频计数器
reg        oclk_r;
assign oclk = oclk_r;
always@(posedge iclk or negedge rst_n)
begin
if(!rst_n)
    begin
	 oclk_r  <= 1'b0;
	 div_cnt <= 0;
	 end
else
    begin
	 div_cnt <= (div_cnt>= div_num-1)?0:div_cnt+1;
	 oclk_r  <= (div_cnt >= ((div_num)>>1))?1'b1:1'b0;
	 end
end
endmodule 